In the past decade, there has been a dramatic increase both in processor speeds and in memory capacity. As a result, the need for networks to handle high-speed transfer of large quantities of data among devices has also increased. Transceivers capable of efficiently receiving and transmitting high-speed data are critical components of these high-speed networks.
At a high level, a transceiver includes a transmitter and a receiver. To reliably process a received data signal, the receiver needs to match its operating characteristics with the characteristics of the received data signal. For example, to minimize data recovery errors, a receiver generates a clock signal to sample the received data signal at times that produce optimal data recovery. To achieve this optimal data recovery, the receiver must lock the sampling clock to the clock of the remote transmitter. A clock data recovery (CDR) unit in the receiver recovers the high-speed clock from the data signal and uses this recovered clock as the sampling clock. The transmitter, on the other hand, transmits data using a clock signal that is locked to the output frequency of a local reference clock.
In many applications such as storage networks, communication devices are connected in loop or daisy chain configurations. Transceivers in these communication devices are often required to re-transmit received data not destined for the device. To allow for data recovery at the destination device, the transmission clock signal used by the transmitter to re-transmit the data must be locked to the sampling clock used by the receiver.
One technique to achieve synchronization between the sampling and the transmission clocks within a transceiver is to have two separate CDR units, one for the receiver and one for the transmitter. A typical CDR unit includes a phase locked loop (PLL) having a voltage controlled oscillator (VCO). When multiple PLLs (and VCOs) are implemented in the same transceiver, cross talk between the two VCOs causes intermodulation that in turn degrades the performance of the transceiver. Intermodulation refers to the condition, also known as injection locking, in which one VCO tracks not only its own reference frequency but the frequency of the other VCO. In addition, the use of multiple VCOs increases the power consumption of the transceiver.
In another technique, the recovered sampling clock is transmitted across the transceiver and used by the transmitter as the transmission clock. The transmission of a high-speed clock across the transceiver requires significant power and also increases cross talk. In addition, any jitter in the sampling clock is introduced into the data stream by the transmitter increasing the possibility of data recovery errors at the destination receiver.
These problems are exacerbated in transceivers that have multiple transmitters and multiple receivers. These transceivers are referred to as multiple channel or multi-channel transceivers. In a multi-channel transceiver, each receiver is capable of receiving a separate data signal. Therefore, each receiver must generate a sampling signal locked to the clock of the remote transmitter. Thus, each receiver must have a separate CDR function. When these transceivers are operating in repeat mode, each transmitter must be locked to the sampling clock of the receiver that received the data to be transmitted. If a PLL is needed for each channel of the multi-channel receiver, the power limits of the transceiver will likely be exceeded.
One example of a multi-channel transceiver is a serializer/deserializer or Serdes transceiver. The transmitter in a Serdes transceiver transmits parallel data in serial order and the receiver converts a received serial data stream back into parallel data. One limitation of Serdes transceivers is the difficulty of testing the device. For example, it is desirable to determine the tolerance of a receiver to jitter and noise. Currently, the testing equipment to perform these tests is costly and cannot be used during production. As a result, a complete view of the operation of a transceiver cannot be developed.
Therefore, a need exists for a communications device having a controllable transmission clock.
A further need exists for a communications device having a transmission clock that can be controlled by an external device.